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181.
Statement for Linked Answer Questions:
Delayed branching can help in the handling of control hazards.[1] For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, [2 marks]
(A) The instruction following the conditional branch instruction in Memory is executed
(B) The first instruction in the fall through path is executed
(C) The first instruction in the taken path is executed
(D) The branch takes longer to execute than any other instruction[2] The following code is to run on a pipelined processor with one branch delay slot
I1: ADD R2 <- R7 +R8
I2: Sub R4 <- R5- R6
I3: ADD R1 <- R2 + R3
I4: STORE Memory [R4]<-R1
BRANCH to Label if R1 = = 0
Which of the instruction I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification ‽ [2 marks]
(A) I1
(B) I2
(C) I3
(D) I4asked in Computer Science And Engineering, 2008
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182.
Consider the following C functions:
int f1 (int n)
{
if (n==0 || n==1)
return n;
else
return (2*f1(n-1) + 3*f1(n-2));
}
intf2 (int n)
{
int i;
int X[n], Y[n], Z[n] ;
X[0] = Y[0] = Z[0] = 0;
X[1] =1, Y[1] =2, Z[1] = 3;
for(i=2; i≤n, i++) {
X[i] = Y[i-1] + Z[i-2];
Y[i] = 2*X[i];
Z[i] = 3*X[i];
}
return X[n];
}
[1] The running time of f1 (n) and f2 (n) are [2 marks]
(A) Θ(n) and Θ(n)
(A) Θ(2n) and Θ(n)
(A) Θ(n) and Θ(2n)
(A) Θ(2n) and Θ(2n)[2] f1(8) and f2(8) return the values [2 marks]
(A) 1661 and 1640
(B) 59 and 59
(C) 1640 and 1640
(D) 1640 and 1661asked in Computer Science And Engineering, 2008
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183.
Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this machine begins as follows:
double ARR [1024] [1024] ;
int i, j ;
/* Initialize array ARR to 0.0 * /
for (i=0;i<1024; i++)
for (j=0;j<1024; j++)
ARR [i] [j] = 0.0;
The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR.
[1] The total size of the tags in the cache directory is [2 marks]
(A) 32Kbits
(B) 34Kbits
(C) 64Kbits
(D) 68Kbits[2] Which of the following array elements has the same cache index as ARR [0] [0]?
[2 marks]
(A) ARR [0] [4]
(B) ARR [4] [0]
(C) ARR [0] [5]
(D) ARR [5] [0][3] The cache hit ratio for this initialization loop is [2 marks]
(A) 0%
(B) 25%
(C) 50%
(D) 75%asked in Computer Science And Engineering, 2008
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184.
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185.
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186.
