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217.

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches
[2 marks]
(A) I only
(B) II only
(C) III only
(D) I, II and III

asked in Computer Science And Engineering, 2008

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218.

Which of the following are NOT true in a pipelined processor?
I. Bypassing can handle all RAW hazards
II. Register renaming can eliminate all register carried WAR hazards
III. Control hazard penalties can be eliminated by dynamic branch prediction
[2 marks]
(A) I and II only
(B) I and III only
(C) II and III only
(D) I, II and III

asked in Computer Science And Engineering, 2008

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219.

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?
I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache
[2 marks]
(A) IV only
(B) I and IV only
(C) I, II and IV only
(D) I, II, III and IV

asked in Computer Science And Engineering, 2008

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220.

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction
[2 marks]
(A) I only
(B) II only
(C) I and II only
(D) I, II and III only

asked in Computer Science And Engineering, 2008

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221.

Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed [2 marks]
(A) I only
(B) II only
(C) III only
(D) II and III only

asked in Computer Science And Engineering, 2008

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222.

For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to [2 marks]
(A) non-uniform distribution of requests
(B) arm starting and stopping inertia
(C) higher capacity of tracks on the periphery of the platter
(D) use of unfair arm scheduling policies

asked in Computer Science And Engineering, 2008

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