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289.

Consider the following C function:
int f(int n)
{static int r = 0;
if (n <= 0) return 1;
if (n > 3)
{r = n;
return f(n-2)+2;
}
return f(n-1)+r;
}
What is the value of f (5)? [2 marks]
(A) 5
(B) 7
(C) 9
(D) 18

asked in Computer Science And Engineering, 2007

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290.

In an unweighted, undirected connected graph, the shortest path from a node S to every other node is computed most efficiently, in terms of time complexity, by [2 marks]
(A) Dijkstra’s algorithm starting from S.
(B) Warshall’s algorithm
(C) Performing a DFS starting from S.
(D) Performing a BFS starting from S.

asked in Computer Science And Engineering, 2007

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291.

Consider a hash table of size seven, with starting index zero, and a hash function
(3x + 4)mod7. Assuming the hash table is initially empty, which of the following is the contents of the table when the sequence 1, 3, 8, 10 is inserted into the table using closed hashing? Note that − denotes an empty location in the table. [2 marks]
(A) 8, −, −, −, −, −, 10
(B) 1, 8, 10, −, −, −, 3
(C) 1, −, −, −, −, −, 3
(D) 1, 10, 8, −, −, −, 3

asked in Computer Science And Engineering, 2007

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292.

The inorder and preorder traversal of a binary tree are
d b e a f c g and a b d e c f g, respectively
The postorder traversal of the binary tree is: [2 marks]
(A) d e b f g c a
(B) e d b g f c a
(C) e d b f g c a
(D) d e f g b c a

asked in Computer Science And Engineering, 2007

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293.

The following postfix expression with single digit operands is evaluated using a stack:
8 2 3 ^ / 2 3 * + 5 1 * -
Note that ^ is the exponentiation operator. The top two elements of the stack after the first * is evaluated are: [2 marks]
(A) 6, 1
(B) 5, 7
(C) 3, 2
(D) 1, 5

asked in Computer Science And Engineering, 2007

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294.

Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 [R2 <- R1 + R0]
MUL R4, R3, R2 [R4 <- R3 * R2]
SUB R6, R5, R4 [R6 <- R5 − R4]
[2 marks]
(A) 7
(B) 8
(C) 10
(D) 14

asked in Computer Science And Engineering, 2007

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