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409.
Statement for Linked Answer Questions :
Let s and t be two vetices in a undirected graph G=(V,E) having distinct positive edge weights. Let [X,Y] be a partition of V such that s ε X and Tε Y. Consider the edge e having the minimum weight amongst all those edges that have one vertex in X and one vertex in Y.[1] (A) The edge e must definitely belong to: [2 marks]
(a) the minimum weighted spanning tree of G
(b) the weighted shortest path from s to t
(c) each path from s to t
(d) the weighted longest path from s to t[2] (B) Let the weight of an edge e denote the congestion on that edge. The congestion on a path is defined to be the maximum of the congestions on the edges of the path. We wish to find the path from s to t having minimum congestion. Which one of the following paths is always such a path of minimum congestion? [2 marks]
(a) a path from s to t in the minimum weighted spanning tree
(b) a weighted shortest path from s to t
(c) an Euler walk from s to t
(d) a Hamiltonian path from s to tasked in Computer Science And Engineering, 2005
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410.
Statement for Linked Answer Questions ::
Consider the following C-function:
double foo (int n) {
int i;
double sum;
if (n==0) return 1.0;
else {
sum = 0.0;
for (i =0; i<n; i++)
sum +=foo(i);
return sum;
} }
[1] (A) The space complexity of the above function is: [2 marks]
(a) O(1)
(b) O(n)
(c) O(n!)
(d) O(nn)[2] (B) Suppose we modify the above function foo() and store the values of foo(i), 0<=I<n, as and when they are computed. With this modification, the time complexity for function foo() is significantly reduced. The space complexity of the modified function would be:
[2 marks]
(a) O(1)
(b) O(n)
(c) O(n2)
(d) O(n!)asked in Computer Science And Engineering, 2005
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411.
Consider the following data path of a CPU.
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.
[1] The instruction “add R0, R1” has the register transfer interpretation R0<= R0+R1. The minimum number of clock cycles needed for execution cycle of this instruction is:
[2 marks]
(a) 2
(b) 3
(c) 4
(d) 5[2] The instruction ‘call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
Rn<= PC+1;
PC<=M[PC];
The minimum number of CPU clock cycles needed during the execution cycle of this instruction is: [2 marks]
(a) 2
(b) 3
(c) 4
(d) 5asked in Computer Science And Engineering, 2005
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412.
last reply by CpjJwWHV • 13 years ago • asked in Computer Science And Engineering, 2005
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413.
last reply by CpjJwWHV • 13 years ago • asked in Computer Science And Engineering, 2005
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414.
The following table has two attributes A and C where A is the primary key and C is the foreign key referencing a with on-delete cascade.
The set of all tuples that must be additionally deleted to preserve referential integrity when the tuple (2,4) is deleted is: [2 marks]A C 2 4 3 4 4 3 5 2 7 2 9 5 6 4
(a) (3,4) and (6,4)
(b) (5,2) and (7,2)
(c) (5,2), (7,2) and (9,5)
(d) (3,4), (4,3) and (6,4)
last reply by CpjJwWHV • 13 years ago • asked in Computer Science And Engineering, 2005
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