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421.

Consider a disk drive with the following specifications:
16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:
[2 marks]
(a) 10
(b) 25
(c) 40
(d) 50

asked in Computer Science And Engineering, 2005

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422.

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4µsec. The byte transfer time between the device interfaces register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode? [2 marks]
(a) 15
(b) 25
(c) 35
(d) 45

asked in Computer Science And Engineering, 2005

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423.

A 5 stage pipelined CPU has the following sequence of stages:
IF – Instruction fetch from instrution memory.
RD – Instruction decode and register read.
EX – Execute: ALU operation for data and address computation.
MA – Data memory access – for write access, the register read at RD state is used.
WB – Register write back.
Consider the following sequence of instructions:
I₁: L R0, loc 1; R0 <=M[loc1]
I₂: A R0, R0 1; R0 <= R0 + R0
I₃: S R2, R0 1; R2 <= R2 - R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I₁? [2 marks]
(a) 8
(b) 10
(c) 12
(d) 15

asked in Computer Science And Engineering, 2005

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424.

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively. [2 marks]
(a) 10, 17
(b) 10, 22
(c) 15, 17
(d) 5, 17

asked in Computer Science And Engineering, 2005

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425.

Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.

(1) A[I] = B[J];
(a) Indirect addressing

(2) while (*A++); (b) Indexed addressing

(3) int temp =*x; (c) Auto increment

[2 marks]
(a) (1, c), (2,b), (3,a)
(b) (1, a), (2,c), (3,b)
(c) (1, b), (2,c), (3,a)
(d) (1, a), (2,b), (3,c)

asked in Computer Science And Engineering, 2005

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426.

Consider a three word machine instruction
ADD A[R0], @B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is:
[2 marks]
(a) 3
(b) 4
(c) 5
(d) 6

last reply by CpjJwWHV • 13 years ago • asked in Computer Science And Engineering, 2005

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