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517.
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
Instruction Operation Instruction Size (in words) MOV R1,5000 R1 <-Memory[5000] 2 MOV R2(R1) R2 <- Memory[(R1)] 1 ADD R2, R3 R2 <- R2 + R3 1 MOV 6000, R2 Memory[6000] <- R2 2 HALT Machine halts 1
[1] Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting form memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be [2 marks]
(a) 1007
(b) 1020
(c) 1024
(d) 1028[2] Let the clock cycles required fro various operations be as follows:
Register to/from memory transfer : 3 clock cyles
ADD with both operands in register : 1 clock cyle
Instruction fetch and decode : 2 clock cycles per word
The total number of clock cycles required to execute the program is [2 marks]
(a) 29
(b) 24
(c) 23
(d) 20asked in Computer Science And Engineering, 2004
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