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709.

The logic circuit used to generate the active low chip select (CS) by an 8085 microprocessor to address a peripheral is shown in Fig. The peripheral will respond to addresses in the range.

[1 mark]
(a) E000-EFFF
(b) 000E-FFFE
(c) 1000-FFFF
(d) 0001-FFF1

asked in Electrical Engineering, 2002

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710.

The line-to-line input voltage to the 3 phase, 50 Hz, ac circuit shown in Fig. is 100 V rms. Assuming that the phase sequence is RYB, the watt meters would read.

[1 mark]
(a) W₁ = 886 W and W₂ = 886 W
(b) W₁ = 500 W and W₂ = 500 W
(c) W₁ = 0 W and W₂ = 1000 W
(d) W₁ = 250 W and W₂ = 750 W

asked in Electrical Engineering, 2002

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711.

The cut-in voltage of both Zener diode D_z and diode D shown in is 0.7 V, while break down voltage of D_z is 3.3 V and reverse breakdown voltage of D is 50 V. the other parameters can be assumed to be the same as those of an ideal diode. The values of the peak output voltage (V₀) are

[1 mark]
(a) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle
(b) 4 V in the positive half cycle and 5 V in the negative half cycle
(c) 3.3 V in both positive and negative half cycles
(d) 4 V in both positive and negative half cycles

asked in Electrical Engineering, 2002

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712.

The forward resistance of the diode shown in Fig is 5W and the remaining parameters are same as those of an ideal diode. The dc component of the source current is

[1mark]
(a) V_m/50π
(b) V_m/50√2π
(c) V_m/100√2π
(d) 2V_m/50π

asked in Electrical Engineering, 2002

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713.

The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in Fig. is 10 kHz. The frequency of the signal available at Q is

[1 mark]
(a) 10 kHz
(b) 2.5 kHz
(c) 20 kHz
(d) 5 kHz

asked in Electrical Engineering, 2002

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714.

A 400V/200V/200V, 50 Hz three winding transformer is connected as shown in Fig. The reading of the voltmeter, V, will be

[1 mark]
(a) 0 V
(b) 400 V
(c) 600 V
(d) 800 V

asked in Electrical Engineering, 2002

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