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211.

The contents (in Hexadecimal) of some of the memory locations in an 8085A based system are given below

Address Contents

...... .......

26FE 01

26FF 02

2700 03

2701 04

2702 05

...... .......

The contents of stack pointer (SP), Program counter(PC) and (H, L) are 2700H, 2100H and 0000H respectively.
When the following sequence of instructions are executed,
2100 H: DAD SP
2101 H: PCHL
the contents of (SP) and (PC) at the end of execution will be
[2 marks]
(A) (PC) = 2102H, (SP) = 2700H
(B) (PC) = 2700H, (SP) = 2700H
(C) (PC) = 2800H, (SP) = 26 FE H
(D) (PC) = 2A02H, (SP)= 2702H

asked in Electrical Engineering, 2008

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212.

The truth table of a monoshot shown in the figure is given in the below

Two monoshots, one positive edge triggered and other negative edge triggered, are connected as shown in the figure. The pulse widths of the two monoshot outputs, Q₁ and Q₂, are T_ON1 and T_ON2 respectively.

The frequency and the duty cycle of the signal at Q1 will respectively be
[2 marks]
(A) f = 1/(T_ON1 + T_ON2), D=1/5
(B) f = 1/(T_ON1 + T_ON2), D=T_ON2/(T_ON1 + T_ON2)
(C) f = 1/T_ON1, D=T_ON1/(T_ON1 + T_ON2)
(D) f = 1/T_ON2, D=T_ON1/(T_ON1 + T_ON2)

asked in Electrical Engineering, 2008

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213.

A 3 line to 8 line decoder, with active low outputs, is used to implement a 3 – variable Boolean function as shown in the figure

The simplified form of Boolean function F (A, B, C) implemented in ‘Product of Sum’ form will be [2 marks]
(A) (X + Z). (X +Y +Z ). (Y + Z)
(B) (X +Z ).(X+Y+Z). (Y +Z)
(C) (X +Y +Z). (X + Y + Z). (X +Y + Z). (X +Y +Z )
(D) (X +Y +Z ). (X+Y+Z ). (X +Y +Z). (X+Y +Z )

asked in Electrical Engineering, 2008

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214.

The block diagrams of two types of half wave rectifiers are shown in the figure. The transfer characteristics of the rectifiers are also shown within the block.

It is desired to make full wave rectifier using above two half – wave rectifiers. The resultant circuit will be [2 marks]

asked in Electrical Engineering, 2008

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215.

In the voltage doubler circuit shown in the figure, the switch ‘S’ is closed at t = 0. Assuming diodes D₁ and D₂ to be ideal, load resistance to be infinite and initial capacitor voltages to be zero, the steady state voltage across capacitors C₁ and C₂ will be

[2 marks]
(A) v_c1= 10V,v_c2 = 5V
(B) v_c1= 10V, v_c2= - 5V
(C) v_c1= 5V, v_c2= 10V
(D) v_c1= 5V, v_c2= - 10V

asked in Electrical Engineering, 2008

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216.

Two perfectly matched silicon transistors are connected as shown in the figure. Assuming the β of the transistors to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current I is

[2 marks]
(A) 0 mA
(B) 3.6 mA
(C) 4.3 mA
(D) 5.7 mA

asked in Electrical Engineering, 2008

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