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169.

The circuit shown in figure converts

[2 marks]
(a) BCD to binary code
(b) Binary to excess – 3 code
(c) Excess – 3 to Gray code
(d) Gray to Binary code

asked in Electronics and Communication Engineering, 2003

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170.

The circuit shown in figure is a 4-bit DAC

The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP AMP is ideal, but all the resistances and the 5V inputs have a tolerance of ±10%. The specification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is [2 marks]
(a) ±35%
(b) ±20%
(c) ±10%
(d) ±5%

asked in Electronics and Communication Engineering, 2003

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171.

The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns.

(P)
(Q)
(R)
(S)

Fanout is minimum
DTL DTL TTL CMOS

Power consumption is minimum
TTL CMOS ECL DTL

Propagation delay is minimum
CMOS ECL TTL TTL

The correct column is [2 marks]
(a) P
(b) Q
(c) R
(d) S

asked in Electronics and Communication Engineering, 2003

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172.

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then [2 marks]
(a) R = 10 ns, S = 40 ns
(b) R = 40 ns, S = 10 ns
(c) R = 10 ns, S = 30 ns
(d) R = 30 ns, S = 10 ns

asked in Electronics and Communication Engineering, 2003

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173.

If the functions W, X, Y and Z are as follows

Then [2 marks]
(a) W = Z, X = Z
(b) W = Z, X = Y
(c) W = Y
(d) W = Y = Z

asked in Electronics and Communication Engineering, 2003

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174.

The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
Y = P ⊕Q ⊕R
Z = RQ+ P R+ QP

The circuit acts as a [2 marks]
(a) 4 bit adder giving P + Q
(b) 4 bit subtractor-giving P - Q
(c) 4 bit subtractor-giving Q - P
(d) 4 bit adder giving P + Q + R

asked in Electronics and Communication Engineering, 2003

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